The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to a carrier head and substrate retainer of a chemical mechanical polishing system.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be a “standard” pad in which the polishing pad surface is a durable, roughened surface, or a fixed-abrasive pad in which abrasive particles are held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles if a standard pad is used, is supplied to the polishing pad.
The effectiveness of a CMP process may be measured by its polishing rate and by the resulting finish (e.g., absence of small-scale roughness) and flatness (e.g., absence of large-scale topography) of the substrate surface. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad.
In the planarization of semiconductor substrate wafers by CMP, it is known to use an annular retaining ring encompassing a wafer being polished for the purpose of preventing lateral movement of the wafer resulting from friction between the wafer and a moving polishing pad. See, e.g., U.S. Pat. No. 5,205,082 of Norm Shendon, et al., the disclosure of which is incorporated herein by reference.
A reoccurring problem in CMP is the so-called “edge-effect”, i.e., the tendency for the edge of the substrate to be polished at a different rate than the center of the substrate. The edge effect typically results in over-polishing (the removal of too much material from the substrate) of the perimeter portion of the substrate, e.g., the outermost five to ten millimeters, although the edge effect may also result in under-polishing. The over-polishing or under-polishing of the substrate perimeter reduces the overall flatness of the substrate, makes the edge of the substrate unsuitable for use in integrated circuits, and decreases the yield.